основные цифровые элементы

В качестве примитивов используются несколько основных элементов. Он был создан только для обучения без каких-либо целей для использования в проектах.

Не могли бы вы подсказать, какие примитивы были бы полезны для изобретения велосипеда для изучения языка?

encode_2

`timescale 1ns / 1ps

module encode_2
(
    input  logic data_0_i,
    input  logic data_1_i,
        
    output logic q_o
);
    
    always_comb begin
        q_o = data_1_i;
    end

endmodule

encode_8

//  |---|---|---|---|
//  |   | 2 | 1 | 0 | < the q's bits
//  |---|---|---|---|
//  | 0 | 0 | 0 | 0 |
//  |---|---|---|---|
//  | 1 | 0 | 0 | 1 |
//  |---|---|---|---|
//  | 2 | 0 | 1 | 0 |
//  |---|---|---|---|
//  | 3 | 0 | 1 | 1 |
//  |---|---|---|---|
//  | 4 | 1 | 0 | 0 |
//  |---|---|---|---|
//  | 5 | 1 | 0 | 1 |
//  |---|---|---|---|
//  | 6 | 1 | 1 | 0 |
//  |---|---|---|---|
//  | 7 | 1 | 1 | 1 |
//  |---|---|---|---|
//    ^
//    a value

`timescale 1ns / 1ps

module encode_8
(
    input  logic         data_0_i,
    input  logic         data_1_i,
    input  logic         data_2_i,
    input  logic         data_3_i,
    input  logic         data_4_i,
    input  logic         data_5_i,
    input  logic         data_6_i,
    input  logic         data_7_i,
    
    output logic [2 : 0] q_o
);
    always_comb begin
        q_o[0] = data_1_i | data_3_i | data_5_i | data_7_i;
        q_o[1] = data_2_i | data_3_i | data_6_i | data_7_i;
        q_o[2] = data_4_i | data_5_i | data_6_i | data_7_i;
    end

endmodule

comp_8_bit

`timescale 1ns / 1ps

module comp_8_bit 
(
    input  logic [7 : 0] a_i,
    input  logic [7 : 0] b_i,
           
    output logic         equal_o,
    output logic         greater_o,
    output logic         lower_o
);

    bit x[7 : 0];  

    always_comb begin
        x[0] = (a_i[0] & b_i[0]) | (~a_i[0] & ~b_i[0]);
        x[1] = (a_i[1] & b_i[1]) | (~a_i[1] & ~b_i[1]);
        x[2] = (a_i[2] & b_i[2]) | (~a_i[2] & ~b_i[2]);
        x[3] = (a_i[3] & b_i[3]) | (~a_i[3] & ~b_i[3]);
        x[4] = (a_i[4] & b_i[4]) | (~a_i[4] & ~b_i[4]);
        x[5] = (a_i[5] & b_i[5]) | (~a_i[5] & ~b_i[5]);
        x[6] = (a_i[6] & b_i[6]) | (~a_i[6] & ~b_i[6]);
        x[7] = (a_i[7] & b_i[7]) | (~a_i[7] & ~b_i[7]);
    
   
        greater_o = (a_i[7] & ~b_i[7]) | 
                    (x[7] & a_i[6] & ~b_i[6]) | 
                    (x[7] & x[6] & a_i[5] & ~b_i[5]) |
                    (x[7] & x[6] & x[5] & a_i[4] & ~b_i[4]) |
                    (x[7] & x[6] & x[5] & x[4] & a_i[3] & ~b_i[3]) |
                    (x[7] & x[6] & x[5] & x[4] & x[3] & a_i[2] & ~b_i[2]) |
                    (x[7] & x[6] & x[5] & x[4] & x[3] & x[2] & a_i[1] & ~b_i[1]) |
                    (x[7] & x[6] & x[5] & x[4] & x[3] & x[2] & x[1] & a_i[0] & ~b_i[0]);

        lower_o = (~a_i[7] & b_i[7]) | 
                  (x[7] & ~a_i[6] & b_i[6]) | 
                  (x[7] & x[6] & ~a_i[5] & b_i[5]) |
                  (x[7] & x[6] & x[5] & ~a_i[4] & b_i[4]) |
                  (x[7] & x[6] & x[5] & x[4] & ~a_i[3] & b_i[3]) |
                  (x[7] & x[6] & x[5] & x[4] & x[3] & ~a_i[2] & b_i[2]) |
                  (x[7] & x[6] & x[5] & x[4] & x[3] & x[2] & ~a_i[1] & b_i[1]) |
                  (x[7] & x[6] & x[5] & x[4] & x[3] & x[2] & x[1] & ~a_i[0] & b_i[0]);
                     
        equal_o = x[7] | x[6] | x[5] | x[4] | x[3] | x[2] |x[1] | x[0];
    end


endmodule

прилавок

`timescale 1ns / 1ps

module counter #
(
    parameter integer COUNTER_MAX_VALUE = 255
)
(
    input  logic                                     clk_i,
    input  logic                                     s_rst_n_i,
    input  logic                                     enable_i,
               
    output logic [$clog2(COUNTER_MAX_VALUE) - 1 : 0] value_o
);
    localparam integer COUNTER_WIDTH = $clog2(COUNTER_MAX_VALUE);
        
    logic [COUNTER_WIDTH - 1 : 0] counter;
    
    always_comb begin
        value_o = counter;
    end
        
    always_ff @ (posedge clk_i) begin
        if (1'h0 == s_rst_n_i) begin
            counter <= {COUNTER_WIDTH{1'h0}};
        end
        else if (1'h1 == enable_i) begin
            if (COUNTER_MAX_VALUE == counter) begin
               counter <= {COUNTER_WIDTH{1'h0}};
            end
            else begin
                counter <= counter + 1'h1;
            end   
        end
    end
    
endmodule

decode_2

`timescale 1ns / 1ps

module decode_2
(
    input  logic data_i,
            
    output logic q_0_o,
    output logic q_1_o
);
    always_comb begin
        q_0_o = ~data_i;
        q_1_o = data_i;
    end

endmodule

decode_8

`timescale 1ns / 1ps

module decode_8
(
    input  logic [2:0] data_i,
            
    output logic       q_0_o,
    output logic       q_1_o,
    output logic       q_2_o,
    output logic       q_3_o,
    output logic       q_4_o,
    output logic       q_5_o,
    output logic       q_6_o,
    output logic       q_7_o
);

    always_comb begin
        q_0_o = ~data_i[2] & ~data_i[1] & ~data_i[0];
        q_1_o = ~data_i[2] & ~data_i[1] & data_i[0];
        q_2_o = ~data_i[2] & data_i[1] & ~data_i[0];
        q_3_o = ~data_i[2] & data_i[1] & data_i[0];
        q_4_o = data_i[2] & ~data_i[1] & ~data_i[0];
        q_5_o = data_i[2] & ~data_i[1] & data_i[0];
        q_6_o = data_i[2] & data_i[1] & ~data_i[0];
        q_7_o = data_i[2] & data_i[1] & data_i[0];
    end
    
endmodule

freq_divider

`timescale 1ns / 1ps

module freq_divider #
(
    parameter integer DIVID_VALUE = 2
)
(
    input  logic clk_i,
    input  logic s_rst_n_i,
           
    output logic clk_o
);
    localparam integer COUNTER_WIDTH = $clog2(DIVID_VALUE);
    
    logic [COUNTER_WIDTH - 1 : 0] counter;
    
    always_comb begin
        clk_o = ({COUNTER_WIDTH{1'h0}} == counter) ? 1'h1 : 1'h0;
    end
    
    always_ff @ (posedge clk_i) begin
        if (1'h0 == s_rst_n_i) begin
            counter <= DIVID_VALUE;
        end
        else begin
            if ({COUNTER_WIDTH{1'h0}} == counter) begin
                counter <= DIVID_VALUE;
            end
            else begin 
                counter <= counter - 1'h1;
            end
        end      
    end

endmodule

ШИМ

`timescale 1ns / 1ps

module pwm #
(
    parameter integer PWM_COUNTER_WIDTH = 8
)
( 
    input  logic                             clk_i,
    input  logic                             s_rst_n_i,
    input  logic                             enable_i,
    
    inout  logic [PWM_COUNTER_WIDTH - 1 : 0] req_value_i,

    output logic                             channel_o  
);

    logic [PWM_COUNTER_WIDTH - 1 : 0] counter;
    
    always_comb begin
        channel_o = (req_value_i != counter) ? 1'h1 : 1'h0;
    end
    
    always_ff @ (posedge clk_i) begin
        if (1'h0 == s_rst_n_i) begin
            counter <= {PWM_COUNTER_WIDTH{1'h0}};
        end
        else if (1'h1 == enable_i) begin
            counter <= counter + 1'h1;
        end
    end

endmodule

gray_decode

`timescale 1ns / 1ps

module gray_decode #
(
    parameter integer DATA_WIDTH = 8
)
(
    input  logic [DATA_WIDTH - 1 : 0] gray_value_i,
    output logic [DATA_WIDTH - 1 : 0] binary_value_o
);

    always_comb begin
        binary_value_o = binary_value_o ^ (gray_value_i >> 1);
    end
    
endmodule

gray_encode

`timescale 1ns / 1ps

module gray_encode #
(
    parameter integer DATA_WIDTH = 8
)
(
    input  logic [DATA_WIDTH - 1 : 0] binary_value_i,
    output logic [DATA_WIDTH - 1 : 0] gray_value_o
);
    
    always_comb begin
        gray_value_o = binary_value_i ^ (binary_value_i >> 1);
    end
    
endmodule

mux_8

`timescale 1ns / 1ps

module mux_8 #
(
    parameter integer DATA_WIDTH = 1
)
(
    input  logic [2 : 0]              select_i,
           
    input  logic [DATA_WIDTH - 1 : 0] data_0_i,
    input  logic [DATA_WIDTH - 1 : 0] data_1_i,
    input  logic [DATA_WIDTH - 1 : 0] data_2_i,
    input  logic [DATA_WIDTH - 1 : 0] data_3_i,
    input  logic [DATA_WIDTH - 1 : 0] data_4_i,
    input  logic [DATA_WIDTH - 1 : 0] data_5_i,
    input  logic [DATA_WIDTH - 1 : 0] data_6_i,
    input  logic [DATA_WIDTH - 1 : 0] data_7_i,
           
    output logic [DATA_WIDTH - 1 : 0] data_o
);  

    always_comb begin
        case (select_i)
            3'h0: begin 
                data_o = data_0_i;
            end
            3'h1: begin 
                data_o = data_1_i;
            end
            3'h2: begin 
                data_o = data_2_i;
            end
            3'h3: begin 
                data_o = data_3_i;
            end
            3'h4: begin 
                data_o = data_4_i;
            end
            3'h5: begin 
                data_o = data_5_i;
            end
            3'h6: begin 
                data_o = data_6_i;
            end
            3'h7: begin 
                data_o = data_7_i;
            end
            default: begin
                data_o = {DATA_WIDTH{1'h0}};
            end
        endcase
    end

endmodule

mux_2

`timescale 1ns / 1ps

module mux_2 #
(
    parameter integer DATA_WIDTH = 1
)
(
    input  logic                      select_i,
           
    input  logic [DATA_WIDTH - 1 : 0] data_0_i,
    input  logic [DATA_WIDTH - 1 : 0] data_1_i,
           
    output logic [DATA_WIDTH - 1 : 0] data_o
);
    
    always_comb begin
        data_o = (1'h0 == select_i) ? data_0_i : data_1_i;
    end

endmodule

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